S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 135

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
7.6 Examples
Programming Notes and Examples
Issue Date: 01/02/13
Example 6: Enable default portrait mode for a 320x240 panel at 4 bpp.
Before switching to portrait mode from landscape mode, display memory should be cleared
to make the user perceived transition smoother. Images in display memory are not rotated
automatically by hardware and a garbled image would be visible for a short period of time
if video memory is not cleared.
If alternate portrait is used then the CLK signal is divided in half to get the PCLK signal. If
the Input Clock Divide bit, in register[02] is set we can simply reset the divider. The result
of this is a PCLK of exactly the same frequency as we used for landscape mode and we can
use the current horizontal and vertical non-display periods. If the Input Clock Divide bit is
not set then we must recalculate the frame rate based on the a PCLK value. In this example
we will bypass recalculation of the horizontal and vertical non-display times (frame rate)
by selecting the default portrait mode scheme.
The display is now configured for portrait mode use. Offset zero into display memory will
corresponds to the upper left corner of the display. The only item to keep in mind is that the
count from the first pixel of one line to the first pixel of the next line (referred to as the
“stride”) is 128 bytes.
1. Calculate and set the Screen 1 Start Word Address register.
2. Calculate the Line Byte Count
3. Enable portrait mode.
OffsetBytes = (Width x BitsPerPixel / 8) - 1 = (256 x 4 / 8) -1 = 127 = 007Fh
(“Width” is the width of the portrait mode display - in this case the next power of two
greater than 240 pixels or 256.)
Set Screen1 Display Start Word Address LSB (REG [0Ch]) to 7Fh and Screen1 Dis-
play Start Word Address MSB (REG[0Dh]) to 00h.
The Line Byte Count also must be based on the power of two width.
LineByteCount = Width x BitsPerPixel / 8 = 256 x 4 / 8 = 128 = 80h.
Set the Line Byte Count (REG[1C]) to 80h.
This example uses the default portrait mode scheme. If we do not change the Portrait
Mode Pixel Clock Select bits then we will not have to recalculate the non-display tim-
ings to correct the frame rate.
Write 80h to the Portrait Mode Register (REG[1Bh]).
X27A-G-002-02
S1D13705
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