S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 471

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
2.1.2 LCD Memory Access Signals
Interfacing to the NEC VR4181A™ Microprocessor
Issue Date: 01/02/13
The S1D13705 requires an addressing range of 128Kbytes. When the VR4181A’s external
LCD controller chip select signal is programmed to a window of that size, the S1D13705
must reside in the VR4181A physical address range of 133E 0000h to 133F FFFFh which
is part of the external ISA memory space.
The signals required for external LCD controller access are listed below and obey ISA
signalling rules.
• A[16:0]
• #UBE
• #LCDCS
• D[15:0]
• #MEMRD
• #MEMWR
• #MEMCS16
• IORDY
• SYSCLK
Once an address in the LCD block of memory is accessed, the LCD chip select #LCDCS is
driven low. The read or write enable signals, #MEMRD or #MEMWR, are driven low for
the appropriate cycle and IORDY is driven low by the S1D13705 to insert wait states into
the cycle. The high byte enable is driven low for 16-bit transfers and high for 8-bit transfers.
Data bus
Read command (active low)
Write command (active low)
Sixteen-bit peripheral capability acknowledge (active low)
Address bus
High byte enable (active low)
LCD controller (S1D13705) chip select (active low)
Ready signal from S1D13705
Optional, prescalable bus clock
X27A-G-013-02
S1D13705
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