MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 1029

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
Freescale Semiconductor
FDIVLCK
FDIV[5:0]
FDIVLD
Offset Module Base + 0x0000
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
5–0
7
6
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms.
BUSCLK frequency. Please refer to
0
7
restore writability to the FDIV field in normal mode.
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
FDIVLCK
= Unimplemented or Reserved
0
6
Figure 28-5. Flash Clock Divider Register (FCLKDIV)
MC9S12G Family Reference Manual, Rev.1.01
Table 28-7. FCLKDIV Field Descriptions
5
0
Section 28.4.4, “Flash Command Operations,”
CAUTION
Table 28-8
0
4
Description
shows recommended values for FDIV[5:0] based on the
0
3
FDIV[5:0]
240 KByte Flash Module (S12FTMRG240K2V1)
2
0
for more information.
0
1
0
0
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