MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 333
MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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Figure 10-2
10.2
This section lists and describes the signals that connect off chip.
10.2.1
Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
10.2.2
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is
the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. If
XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If
OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 kΩ and the XTAL
pin is pulled down by an internal resistor of approximately 700 kΩ.
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Signal Description
RESET
EXTAL and XTAL
shows a block diagram of the XOSCLCP.
Detector
Peak
EXTAL
MC9S12G Family Reference Manual, Rev.1.01
Figure 10-2. XOSCLCP Block Diagram
VSS
Gain Control
C1
Ceramic Resonators
Quartz Crystals
Rf
or
VDD = 1.8 V
VSS
Monitor
Clock
S12 Clock, Reset and Power Management Unit (S12CPMU)
VSS
OSCCLK_LCP
XTAL
C2
monitor fail
333
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