MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 368

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12 Clock, Reset and Power Management Unit (S12CPMU)
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PEE mode is as follows:
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
10.4.6.3
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is
based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps:
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows:
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
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4. Clear all flags in the CPMUFLG register to be able to detect any future status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
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1. Make sure the PLL configuration is valid.
2. Enable the external oscillator (OSCE bit)
3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1).
4. Clear all flags in the CPMUFLG register to be able to detect any status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
6. Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0)
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This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
The OSCCLK provided to the MSCAN module is off.
PLLSEL is set automatically and the Bus Clock is switched back to the PLLCLK.
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
The OSCCLK provided to the MSCAN module is off.
PLL Bypassed External Mode (PBE)
MC9S12G Family Reference Manual,
Rev.1.01
Freescale Semiconductor