MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 505

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
16.3.3
The following section details the organization of the receive and transmit message buffers and the
associated control registers.
To simplify the programmer interface, the receive and transmit message buffers have the same outline.
Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last
two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an
internal timer after successful transmission or reception of a message. This feature is only available for
transmit and receiver buffers, if the TIME bit is set (see
(CANCTL0)”).
The time stamp register is written by the MSCAN. The CPU can only read these registers.
Freescale Semiconductor
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
AM[7:0]
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
7-0
Programmer’s Model of Message Storage
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
Table 16-25. CANIDMR4–CANIDMR7 Register Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
Description
Section 16.3.2.1, “MSCAN Control Register 0
Freescale’s Scalable Controller Area Network (S12MSCANV3)
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