MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 402

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Analog-to-Digital Converter (ADC10B12CV2)
12.3.2
This section describes in address order all the ADC10B12C registers and their individual bits.
12.3.2.1
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
402
Address
0x0028 -
Module Base + 0x0000
0x0024
0x0026
0x002F
WRAP[3-0]
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
3-0
W
R
ATDDR10
ATDDR11
Reserved
Unimple-
mented
Register Descriptions
Name
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
7
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
0
0
0
W
W
W
R
R
R
Figure 12-2. ADC10B12C Register Summary (Sheet 3 of 3)
= Unimplemented or Reserved
0
0
6
Bit 7
0
0
0
0
1
1
0
Table 12-2. Multi-Channel Wrap Around Coding
Figure 12-3. ATD Control Register 0 (ATDCTL0)
MC9S12G Family Reference Manual,
Table 12-1. ATDCTL0 Field Descriptions
= Unimplemented or Reserved
0
0
1
1
0
0
5
0
0
and
and
6
0
See
See
Section 12.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 12.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 12.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 12.3.2.12.1, “Left Justified Result Data (DJM=0)”
0
1
0
1
0
1
5
0
0
0
4
Multiple Channel Conversions (MULT = 1)
Description
Wraparound to AN0 after Converting
0
4
WRAP3
Table
1
3
12-2.
Reserved
Rev.1.01
3
0
AN1
AN2
AN3
AN4
AN5
WRAP2
1
2
1
2
0
WRAP1
Freescale Semiconductor
1
1
0
1
WRAP0
Bit 0
1
0
0