MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 877

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

All assigned bits in the FERCNFG register are readable and writable.
25.3.2.7
The FSTAT register reports the operational status of the Flash module.
1
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Freescale Semiconductor
Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see
Offset Module Base + 0x0005
Offset Module Base + 0x0006
Reset
DFDIE
SFDIE
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
1
0
W
W
R
R
CCIF
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
1 An interrupt will be requested whenever the SFDIF flag is set (see
Flash Status Register (FSTAT)
0
0
1
7
7
Figure 25-10. Flash Error Configuration Register (FERCNFG)
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 25-11. Flash Status Register (FSTAT)
Table 25-14. FERCNFG Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
ACCERR
5
0
0
5
0
FPVIOL
0
0
0
4
4
Description
MGBUSY
0
0
0
3
3
Section
Section
Section
96 KByte Flash Module (S12FTMRG96K1V1)
RSVD
25.3.2.8)
2
0
0
2
0
25.3.2.8)
25.3.2.8)
DFDIE
0
0
1
1
1
MGSTAT[1:0]
Section
SFDIE
0
0
0
0
1
25.6).
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