MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 197

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
2.4.3.47
2.4.3.48
Freescale Semiconductor
Address 0x026E (G1, G2)
Address 0x026E (G3)
Address 0x026F (G1, G2)
Address 0x026F (G3)
Read: Anytime
Write: Anytime
Read: Anytime
Field
PIEJ
Reset
Reset
Reset
Reset
7-0
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
W
W
W
R
R
R
R
Port J interrupt enable—
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
PIEJ7
PIFJ7
Port J Interrupt Enable Register (PIEJ)
0
0
0
Port J Interrupt Flag Register (PIFJ)
0
0
0
7
7
7
7
PIEJ6
PIFJ6
0
0
0
0
0
0
6
6
6
6
Figure 2-47. Port J Interrupt Enable Register (PIEJ)
Figure 2-48. Port J Interrupt Flag Register (PIFJ)
Table 2-74. PIEJ Register Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
PIEJ5
PIFJ5
0
0
0
0
0
0
5
5
5
5
PIEJ4
PIFJ4
0
0
0
0
0
0
4
4
4
4
Description
PIEJ3
PIEJ3
PIFJ3
PIFJ3
0
0
0
0
3
3
3
3
PIEJ2
PIEJ2
PIFJ2
PIFJ2
2
0
2
0
2
0
2
0
Port Integration Module (S12GPIMV0)
Access: User read/write
Access: User read/write
Access: User read/write
Access: User read/write
PIEJ1
PIEJ1
PIFJ1
PIFJ1
0
0
0
0
1
1
1
1
PIEJ0
PIEJ0
PIFJ0
PIFJ0
0
0
0
0
0
0
0
0
197
1
1
1
1