MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 311

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Field3 Bits in Compressed Pure PC Modes
Each time that PC[17:6] differs form the previous base PC[17:6], then a new base address is stored. The
base address zero value is the lowest address in the 64 address range
The first line of the trace buffer always gets a base PC address, this applies also on rollover.
8.4.5.5
The data stored in the Trace Buffer can be read provided the DBG module is not armed, is configured for
tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer
is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word
write to DBGTB when the module is disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid lines can be determined. DBGCNT does not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0,
otherwise it points to the line with the oldest entry. In compressed Pure PC mode on rollover the line with
the oldest data entry may also contain newer data entries in fields 0 and 1. Thus if rollover is indicated by
the TBF bit, the line status must be decoded using the INF bits in field3 of that line. If both INF bits are
clear then the line contains only entires from before the last rollover.
If INF0=1 then field 0 contains post rollover data but fields 1 and 2 contain pre rollover data.
If INF1=1 then fields 0 and 1 contain post rollover data but field 2 contains pre rollover data.
The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables
an interrupted trace buffer read sequence to be easily restarted from the oldest data entry.
The least significant word of line is read out first. This corresponds to the fields 1 and 0 of
next word read returns field 2 in the least significant bits [3:0] and “0” for bits [15:4].
Reading the Trace Buffer while the DBG module is armed returns invalid data and no shifting of the RAM
pointer occurs.
8.4.5.6
The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system
reset occur, the trace session information from immediately before the reset occurred can be read out and
the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
INF1
0
0
1
1
Reading Data from Trace Buffer
Trace Buffer Reset State
INF0
0
1
0
1
Table 8-40. Compressed Pure PC Mode Field 3 Information Bit Encoding
Base PC address TB[17:0] contains a full PC[17:0] value
Trace Buffer[5:0] contain incremental PC relative to base address zero value
Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value
Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value
MC9S12G Family Reference Manual, Rev.1.01
TRACE BUFFER ROW CONTENT
S12S Debug Module (S12SDBG)
Table
8-36. The
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