MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 590

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Communication Interface (S12SCIV5)
indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control
register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
18.4.6.3
The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust
for baud rate mismatch, the RT clock (see
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic
1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Figure 18-17
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
590
RT CLock Count
•
•
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Reset RT Clock
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
RT Clock
Samples
RXD
Data Sampling
summarizes the results of the start bit verification samples.
1
RT3, RT5, and RT7 Samples
1
1
1
000
001
010
011
100
101
110
111
1
MC9S12G Family Reference Manual,
1
Figure 18-21. Receiver Data Sampling
Qualification
Start Bit
Table 18-17. Start Bit Verification
1
1
Figure
0
0
18-21) is re-synchronized:
Start Bit Verification
Verification
Start Bit
0
Yes
Yes
Yes
Yes
No
No
No
No
0
Start Bit
0
Sampling
Rev.1.01
Data
0
0
Noise Flag
0
1
1
0
1
0
0
0
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