MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 315

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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8.5.2
A trigger is generated if a given sequence of 3 code events is executed.
Scenario 1 is possible with S12SDBGV1 SCR encoding
8.5.3
A trigger is generated if a given sequence of 2 code events is executed.
A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry
into a range (COMPA,COMPB configured for range mode)
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
SCR1=0011
SCR1=0011
SCR1=0111
SCR1=0010
State1
State1
State1
State1
Scenario 1
Scenario 2
M1
M1
M01
M2
SCR2=0010
SCR2=0101
SCR2=0101
SCR2=0011
MC9S12G Family Reference Manual, Rev.1.01
State2
State2
State2
State2
Figure 8-29. Scenario 2b
Figure 8-28. Scenario 2a
Figure 8-30. Scenario 2c
Figure 8-27. Scenario 1
M2
M2
M2
M0
Final State
Final State
Final State
SCR3=0111
State3
M0
Final State
S12S Debug Module (S12SDBG)
315

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