MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 482

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.1.1
16.1.2
482
Wake-Up Interrupt Req.
Transmit Interrupt Req.
Receive Interrupt Req.
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Errors Interrupt Req.
Oscillator Clock
Glossary
Block Diagram
Bus Clock
oscillator clock
CAN clock
bus clock
CPU bus
CAN bus
CRC
FIFO
ACK
CAN
EOF
SOF
IFS
MSCAN
MC9S12G Family Reference Manual,
Acknowledge of CAN message
Controller Area Network
Cyclic Redundancy Code
End of Frame
First-In-First-Out Memory
Inter-Frame Sequence
Start of Frame
CPU related read/write data bus
CAN protocol related serial bus
Direct clock from external oscillator
CPU bus related clock
CAN protocol related clock
Figure 16-1. MSCAN Block Diagram
MUX
Configuration
CANCLK
Table 16-2. Terminology
Registers
Control
Status
and
Presc.
Tq Clk
Wake-Up
Rev.1.01
Low Pass Filter
Message
Buffering
Receive/
Transmit
Filtering
Engine
and
Freescale Semiconductor
RXCAN
TXCAN

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