MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 245

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

5.4.4
On S12G devices, the CPU and the BDM are not able to access the memory in parallel. An arbitration
occurs whenever both modules attempt a memory access at the same time. CPU accesses are handled with
higher priority than BDM accesses unless the BDM module has been stalled for more then 128 bus cycles.
In this case the pending BDM access will be processed immediately.
5.4.5
The S12GMMC does not generate any interrupts.
Freescale Semiconductor
(NVMRES=1)
(NVMRES=0)
0x3C000-
0x04000-
0x04000-
0x08000-
0x08000-
0x20000-
0x28000-
0x30000-
0x34000-
0x38000-
0x3BFFF
0x07FFF
0x07FFF
0x0FFFF
0x1FFFF
0x27FFF
0x2FFFF
0x33FFF
0x37FFF
0x3FFFF
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Prioritization of Memory Accesses
Interrupts
S12GN16
Reserved
16k
S12GN32
32k
Unimplemented
MC9S12G Family Reference Manual, Rev.1.01
Internal NVM Resources (for details refert to section FTMRG)
Table 5-8. Global Address Ranges
S12GN48
Reserved
S12G48,
48k
S12G64
64k
Reserved
S12G96
96k
S12G Memory Map Controller (S12GMMCV1)
S12G128
Flash
128k
Reserved
S12G192
192k
S12G240
240k
245