MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 769

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

23.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
Freescale Semiconductor
Address
Offset Module Base + 0x0000
Reset
& Name
0x000D
0x000E
0x000F
FRSV2
FRSV3
FRSV4
0x0010
0x0011
FRSV5
0x0012
FRSV6
0x0013
FRSV7
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
FOPT
W
R
FDIVLD
Flash Clock Divider Register (FCLKDIV)
0
7
W
W
W
W
W
W
W
R
R
R
R
R
R
R
NV7
7
0
0
0
0
0
0
FDIVLCK
Figure 23-4. FTMRG48K1 Register Summary (continued)
= Unimplemented or Reserved
0
6
Figure 23-5. Flash Clock Divider Register (FCLKDIV)
NV6
= Unimplemented or Reserved
6
0
0
0
0
0
0
MC9S12G Family Reference Manual, Rev.1.01
5
0
NV5
5
0
0
0
0
0
0
0
4
NV4
4
0
0
0
0
0
0
0
3
NV3
FDIV[5:0]
3
0
0
0
0
0
0
48 KByte Flash Module (S12FTMRG48K1V1)
2
0
NV2
2
0
0
0
0
0
0
NV1
0
1
1
0
0
0
0
0
0
NV0
0
0
0
0
0
0
0
0
0
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