MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 279

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 8
S12S Debug Module (S12SDBG)
Revision History
8.1
The S12SDBG module provides an on-chip trace buffer with flexible triggering capability to allow
non-intrusive debug of application software. The S12SDBG module is optimized for S12SCPU
debugging.
Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user
configures the S12SDBG module for a debugging session over the BDM interface. Once configured the
S12SDBG module is armed and the device leaves BDM returning control to the user program, which is
then monitored by the S12SDBG module. Alternatively the S12SDBG module can be configured over a
serial interface using SWI routines.
8.1.1
COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt.
Freescale Semiconductor
Revision Number
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
02.00
02.01
02.02
02.03
02.04
02.05
02.06
02.07
Introduction
Glossary Of Terms
09.AUG..2007
10.AUG..2007
29.AUG..2007
31.JUL..2007
13.DEC.2007
17.OCT.2007
19.OCT.2007
22.NOV.2007
Date
MC9S12G Family Reference Manual, Rev.1.01
Author
State sequencer encoding enhanced
Simultaneous TRIG and ARM setting updated
Pure PC replaced with Compressed Pure PC Mode
Enhanced compressed Pure PC mode description
Added CompA size & databus byte compare enhancement
DBGSCR1 encoding 1101 added.
CompA functional description improved
Swapped NDB and SZ in DBGACTL to match DBGBCTL
Reverted to final state transition priority
Table 8-33
Table 8-39
Section 8.4.5.6, “Trace Buffer Reset State
Section 8.5, “Application Information
information
DB byte access configuration corrected
Correction
Summary of Changes
Added application
Added NOTE
8.4.5.2.4
279