MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 142

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Port Integration Module (S12GPIMV0)
142
PAD13
PAD12
PAD11
PAD10
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
• 64/100 LQFP: The inverting analog input signal AMPM0 of the DAC0 module is mapped to this pin if
• 64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN13
• 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
• 64/100 LQFP: The ADC analog input channel signal AN12 and the related digital trigger input are
• 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
• 48/64/100 LQFP: The buffered analog output signal AMP0 of the DAC0 module is mapped to this pin
• 48 LQFP: The unbuffered analog output signal DACU0 of the DAC0 module is mapped to this pin if the
• 48/64 LQFP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when
• 48/64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN11
• 48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
• 48/64 LQFP: The buffered analog output signal AMP1 of the DAC1 module is mapped to this pin if the
• 100 LQFP: The buffered analog output signal AMP1 of the DAC1 module is mapped to this pin if the
• 48/64 LQFP: The unbuffered analog output signal DACU1 of the DAC1 module is mapped to this pin
• 48/64 LQFP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin
• 48/64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN10
• 48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
the DAC is operating in “unbuffered DAC with operational amplifier” or “operational amplifier only”
mode. If this pin is used with the DAC then the digital input buffer is disabled.
and the related digital trigger input are mapped to this pin. The ADC function has no effect on the
output state. The input buffer is controlled by the related ATDDIEN bit and the ADC trigger function.
64/100 LQFP: GPO
mapped to this pin. The ADC function has no effect on the output state. The input buffer is controlled
by the related ATDDIEN bit and the ADC trigger function.
64/100 LQFP: GPO
if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational amplifier” or “operational
amplifier only” mode. If this pin is used with the DAC then the digital I/O function and pull device are
disabled.
DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital output
function and pull device are disabled.
used with the ACMP function. The ACMP function has no effect on the output state. The input buffer
is controlled by the ACDIEN bit .
and the related digital trigger input are mapped to this pin. The ADC function has no effect on the
output state. The input buffer is controlled by the related ATDDIEN bit and the ADC trigger function.
48 LQFP: AMP0 | DACU0 > GPO
64/100 LQFP: AMP0 > GPO
DAC is operating in “buffered DAC” mode. If this pin is used with the DAC then the digital output
function and pull device are disabled.
DAC is operating in “buffered DAC”, “unbuffered DAC with operational amplifier” or “operational
amplifier only” mode. If this pin is used with the DAC then the digital I/O function and pull device are
disabled.
if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital output
function and pull device are disabled.
when used with the ACMP function. The ACMP function has no effect on the output state. The input
buffer is controlled by the ACDIEN bit .
and the related digital trigger input are mapped to this pin. The ADC function has no effect on the
output state. The input buffer is controlled by the related ATDDIEN bit and the ADC trigger function.
48/64 LQFP: AMP1 | DACU1 > GPO
100 LQFP: AMP1 > GPO
MC9S12G Family Reference Manual,
Table 2-16. Port
AD
Pins AD15-8
Rev.1.01
Freescale Semiconductor