MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 355

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Read: Anytime
Write: Anytime if APIFE=0. Else writes have no effect.
The period can be calculated as follows depending on logical value of the APICLK bit:
Freescale Semiconductor
0x02F4
0x02F5
APIR[15:0]
Reset
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Field
15-0
W
W
R
R
APICLK=0: Period = 2*(APIR[15:0] + 1) * f
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock period
APIR15
APIR7
Figure 10-20. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
Autonomous Periodical Interrupt Rate Bits — These bits define the time-out period of the API. See
Table 10-20
Figure 10-21. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
0
0
7
7
For APICLK bit clear the first time-out period of the API will show a latency
time between two to three f
release when the API feature gets enabled (APIFE bit set)
APICLK
Table 10-20. Selectable Autonomous Periodical Interrupt Periods
0
0
0
0
APIR14
for details of the effect of the autonomous periodical interrupt rate bits.
Table 10-19. CPMUAPIRH / CPMUAPIRL Field Descriptions
APIR6
= Unimplemented or Reserved
0
0
6
6
MC9S12G Family Reference Manual, Rev.1.01
APIR13
APIR5
APIR[15:0]
5
0
5
0
0000
0001
0002
0003
ACLK
APIR12
APIR4
cycles due to synchronous clock gate
NOTE
0
0
4
4
ACLK
Description
S12 Clock, Reset and Power Management Unit (S12CPMU)
APIR11
APIR3
0
0
3
3
Selected Period
0.2 ms
0.4 ms
0.6 ms
0.8 ms
APIR10
APIR2
.
1
1
1
1
2
0
2
0
APIR9
APIR1
0
0
1
1
APIR8
APIR0
0
0
0
0
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