MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 249

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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6.2
The INT module has no external signals.
6.3
This section provides a detailed description of all registers accessible in the INT module.
6.3.1
This section describes in address order all the INT registers and their individual bits.
6.3.1.1
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: 0x0120
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
R
External Signal Description
Memory Map and Register Definition
Peripheral
Interrupt Requests
Register Descriptions
Interrupt Vector Base Register (IVBR)
1
7
1
6
Figure 6-2. Interrupt Vector Base Register (IVBR)
Non I bit Maskable Channels
I bit Maskable Channels
MC9S12G Family Reference Manual, Rev.1.01
Figure 6-1. INT Block Diagram
5
1
1
4
IVB_ADDR[7:0]
1
3
Interrupt
Requests
2
1
Wake Up
CPU
IVBR
Address
Vector
Interrupt Module (S12SINTV1)
1
1
1
0
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