MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 558

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Pulse-Width Modulator (S12PWM8B8CV2)
To calculate the output frequency in left aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register
for that channel.
As an example of a left aligned output, consider the following case:
The output waveform generated is shown in
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This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
PWMx Duty Cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
— Polarity = 1 (PPOLx = 1)
Clock Source = E, where E = 10 MHz (100 ns period)
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx Frequency = 10 MHz/4 = 2.5 MHz
PWMx Period = 400 ns
PWMx Duty Cycle = 3/4 *100% = 75%
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
Changing the PWM output mode from left aligned to center aligned output
(or vice versa) while channels are operating can cause irregularities in the
PWM output. It is recommended to program the output mode before
enabling the PWM channel.
PPOLx = 0
PPOLx = 1
E = 100 ns
Figure 17-18. PWM Left Aligned Output Example Waveform
Figure 17-17. PWM Left Aligned Output Waveform
MC9S12G Family Reference Manual,
PWMDTYx
Period = 400 ns
Figure
Period = PWMPERx
Duty Cycle = 75%
NOTE
17-18.
Rev.1.01
Freescale Semiconductor