MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 717

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
FDIVLCK
FDIV[5:0]
FDIVLD
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
5–0
7
6
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms.
BUSCLK frequency. Please refer to
restore writability to the FDIV field in normal mode.
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
1
2
BUSCLK is Greater Than this value.
BUSCLK is Less Than or Equal to this value.
BUSCLK Frequency
MIN
10.6
11.6
12.6
13.6
14.6
15.6
1.0
1.6
2.6
3.6
4.6
5.6
6.6
7.6
8.6
9.6
1
Table 22-8. FDIV values for various BUSCLK Frequencies
(MHz)
MAX
10.6
11.6
12.6
13.6
14.6
15.6
16.6
1.6
2.6
3.6
4.6
5.6
6.6
7.6
8.6
9.6
MC9S12G Family Reference Manual, Rev.1.01
Table 22-7. FCLKDIV Field Descriptions
2
FDIV[5:0]
Section 22.4.4, “Flash Command Operations,”
0x0A
0x0B
0x0C
0x0D
0x0E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0F
CAUTION
Table 22-8
Description
BUSCLK Frequency
MIN
16.6
17.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
shows recommended values for FDIV[5:0] based on the
1
(MHz)
MAX
17.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
25.6
32 KByte Flash Module (S12FTMRG32K1V1)
2
FDIV[5:0]
for more information.
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
717