MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 251

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the CPU vector request), the vector address supplied
to the CPU will default to that of the spurious interrupt vector.
6.4.3
The INT module supports three system reset exception request types (please refer to the Clock and Reset
generator module for details):
6.4.4
The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon
request by the CPU is shown in
1
2
3
Freescale Semiconductor
(Vector base + 0x00F0–0x0082) Device specific I bit maskable interrupt sources (priority determined by the low byte of the
16 bits vector address based
D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt
D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt
1. Pin reset, power-on reset or illegal address reset, low voltage reset (if applicable)
2. Clock monitor reset request
3. COP watchdog reset request
(Vector base + 0x00F8)
(Vector base + 0x00F6)
(Vector base + 0x00F4)
(Vector base + 0x00F2)
(Vector base + 0x0080)
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Vector Address
0xFFFE
0xFFFC
0xFFFA
Reset Exception Requests
Exception Priority
Care must be taken to ensure that all interrupt requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0080)).
1
Pin reset, power-on reset, illegal address reset, low voltage reset (if applicable)
Clock monitor reset
COP watchdog reset
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
X bit maskable interrupt request (XIRQ or D2D error interrupt)
IRQ or D2D interrupt request
vector address, in descending order)
Spurious interrupt
Table 6-4. Exception Vector Map and Priority
Table
MC9S12G Family Reference Manual, Rev.1.01
6-4.
NOTE
3
Source
2
Interrupt Module (S12SINTV1)
251