MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 645

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Read: Anytime
Write: Anytime.
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
20.3.2.11 Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
Freescale Semiconductor
C7I:C0I
PR[2:0]
Reset
TCRE
Field
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
TOI
7:0
unavailable bits return a zero
7
3
2
W
R
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1,
Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock", for
Note: This bit and feature is available only when channel 7 exists. If channel 7 doesn’t exist, this bit is reserved.
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in
TOI
0
7
TOF will never be set when TCNT is reset from 0xFFFF to 0x0000.
a more detail explanation please refer to
Writing to reserved bit has no effect. Read from reserved bit return a zero.
= Unimplemented or Reserved
Figure 20-19. Timer System Control Register 2 (TSCR2)
0
0
6
Table
MC9S12G Family Reference Manual, Rev.1.01
Table 20-14. TSCR2 Field Descriptions
Table 20-13. TIE Field Descriptions
20-15.
5
0
0
0
0
4
Section 20.4.3, “Output Compare
Description
Description
TCRE
0
3
PR2
2
0
Timer Module (TIM16B8CV3)
PR1
0
1
PR0
0
0
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