MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 290

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12S Debug Module (S12SDBG)
control logic as depicted in
the comparator enable bit in the associated DBGXCTL control register.
The priorities described in
final state has priority followed by the match on the lower channel number (0,1,2). Thus with
SC[3:0]=1101 a simultaneous match0/match1 transitions to final state.
8.3.2.7.2
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and DBG is not armed.
290
Address: 0x0027
SC[3:0]
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
3–0
W
R
These bits select the targeted next state whilst in State1, based upon the match event.
0
0
7
Debug State Control Register 2 (DBGSCR2)
Figure 8-10. Debug State Control Register 2 (DBGSCR2)
= Unimplemented or Reserved
0
0
6
Table 8-35
Figure 8-1
Table 8-15. State1 Sequencer Next State Selection
Either Match0 or Match2 to Final State........Match1 to State2
Table 8-14. DBGSCR1 Field Descriptions
MC9S12G Family Reference Manual,
Description (Unspecified matches have no effect)
dictate that in the case of simultaneous matches, a match leading to
and described in 8.3.2.8.1. Comparators must be enabled by setting
5
0
0
Match1 to State3.........Match0 to Final State
Match0 to State2....... Match1 to State3
Match0 to State2....... Match2 to State3
Either Match0 or Match1 to State2
Any match to Final State
0
0
4
Match2 to State2
Match1 to State2
Match1 to State3
Match0 to State3
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SC3
0
3
Rev.1.01
SC2
2
0
Freescale Semiconductor
SC1
0
1
SC0
0
0