MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 304

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12S Debug Module (S12SDBG)
8.4.3
Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register
TAG bits select the match mode. The modes are described in the following sections.
8.4.3.1
When configured for forced matching, a comparator channel match can immediately initiate a transition
to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control
register for the current state determines the next state. Forced matches are typically generated 2-3 bus
cycles after the final matching address bus cycle, independent of comparator RWE/RW settings.
Furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an
opcode address typically precedes a tagged match at the same address.
8.4.3.2
If a CPU taghit occurs a transition to another state sequencer state is initiated and the corresponding
DBGSR flags are set. For a comparator related taghit to occur, the DBG must first attach tags to
instructions as they are fetched from memory. When the tagged instruction reaches the execution stage of
the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition.
8.4.3.3
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing
to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into
the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the
session and issues a forced breakpoint request to the CPU.
It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of
the current state of ARM.
8.4.3.4
In case of simultaneous matches the priority is resolved according to
suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher
priority. The priorities described in
pointing to final state has highest priority followed by the lower channel number (0,1,2).
304
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Priority
Highest
Lowest
Match Modes (Forced or Tagged)
Forced Match
Tagged Match
Immediate Trigger
Channel Priorities
Channel pointing to Final State
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
Source
TRIG
MC9S12G Family Reference Manual,
Table 8-35
Table 8-35. Channel Priorities
dictate that in the case of simultaneous matches, the match
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Rev.1.01
Enter Final State
Table
Action
8-35. The lower priority is
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