MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 514

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale’s Scalable Controller Area Network (S12MSCANV3)
In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
1
16.3.3.5
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see
“MSCAN Control Register 0
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
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514
Module Base + 0x00XD
Module Base + 0x00XE
Read: Anytime when TXEx flag is set (see
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Write: Anytime when TXEx flag is set (see
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Read: Anytime when TXEx flag is set (see
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Write: Unimplemented
•
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Reset:
Reset:
The transmission buffer with the lowest local priority field wins the prioritization.
W
W
R
R
Time Stamp Register (TSRH–TSRL)
TSR15
PRIO7
0
7
7
x
Figure 16-37. Time Stamp Register — High Byte (TSRH)
Figure 16-36. Transmit Buffer Priority Register (TBPR)
TSR14
PRIO6
0
x
6
6
(CANCTL0)”). In case of a transmission, the CPU can only read the time
MC9S12G Family Reference Manual,
Section 16.3.2.7, “MSCAN Transmitter Flag Register
Section 16.3.2.7, “MSCAN Transmitter Flag Register
Section 16.3.2.7, “MSCAN Transmitter Flag Register
TSR13
PRIO5
0
5
5
x
TSR12
PRIO4
0
x
4
4
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
TSR11
PRIO3
0
3
3
x
Rev.1.01
PRIO2
TSR10
2
0
2
x
(CANTFLG)”) and the
(CANTFLG)”) and the
(CANTFLG)”) and the
Freescale Semiconductor
Access: User read/write
Access: User read/write
PRIO1
TSR9
Section 16.3.2.1,
0
1
1
x
PRIO0
TSR8
0
0
0
x
1
1