MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 1120

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Detailed Register Address Map
Appendix B
Detailed Register Address Map
Revision History
B.1
The following tables show the detailed register map of the MC9S12G-Family.
0x0000–0x0009 Port Integration Module (PIM) Map 1 of 6
1120
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
Rev 0.05
Rev 0.06
Rev 0.07
Rev 0.08
Number
Version
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Detailed Register Map
PORTC
PORTD
PORTB
PORTE
PORTA
DDRA
DDRB
DDRC
DDRD
DDRE
Name
30-Aug-2010
18-Oct-2010
9-Nov-2010
4-Dec-2010
This is a summary of all register bits implemented on MC9S12G devices.
Each member of the MC9S12G-Family implements the subset of registers,
which is associated with its feature set (see
Revision
Date
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
DDRC7
DDRD7
DDRA7
DDRB7
Bit 7
PC7
PD7
PB7
PA7
0
0
• Updated ATDCTL2 register in
• Updated CPMUOSC register in
• Updated ADC registers in
• Updated CPMU registers in
• Updated PIM registers in
MC9S12G Family Reference Manual,
DDRC6
DDRD6
DDRA6
DDRB6
Bit 6
PB6
PC6
PD6
PA6
0
0
DDRA5
DDRB5
DDRC5
DDRD5
Bit 5
PB5
PC5
PD5
PA5
0
0
NOTE
Appendix B, “Detailed Register Address
Appendix B, “Detailed Register Address
Appendix B, “Detailed Register Address
Description of Changes
Appendix B, “Detailed Register Address
DDRA4
DDRB4
DDRC4
DDRD4
Appendix B, “Detailed Register Address
Bit 4
PB4
PC4
PD4
PA4
Table
0
0
1-1).
Rev.1.01
DDRA3
DDRB3
DDRC3
DDRD3
Bit 3
PB3
PC3
PD3
PA3
0
0
DDRA2
DDRB2
DDRC2
DDRD2
Bit 2
PC2
PD2
PA2
PB2
0
0
Freescale Semiconductor
Map”.
Map”.
DDRC1
DDRD1
DDRA1
DDRB1
DDRE1
Map”.
Bit 1
PC1
PD1
PB1
PE1
PA1
Map”.
Map”.
DDRC0
DDRD0
DDRE0
DDRA0
DDRB0
Bit 0
PA 0
PC0
PD0
PB0
PE0