MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 316

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12S Debug Module (S12SDBG)
8.5.4
A trigger is generated immediately when one of up to 3 given events occurs
Scenario 3 is possible with S12SDBGV1 SCR encoding
8.5.5
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B
and event B must be followed by event A. 2 consecutive occurances of event A without an intermediate
event B cause a trigger. Similarly 2 consecutive occurances of event B without an intermediate event A
cause a trigger. This is possible by using CompA and CompC to match on the same address as shown.
This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2
comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown.
The advantage of using only 2 channels is that now range comparisons can be included (channel0)
316
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Scenario 3
Scenario 4
SCR3=0001
SCR3=1110
SCR1=0100
SCR1=0110
Figure 8-33. Scenario 4b (with 2 comparators)
SCR1=0000
State1
MC9S12G Family Reference Manual,
Figure 8-32. Scenario 4a
Figure 8-31. Scenario 3
M1
M2
State1
State1
State 3
State 3
M012
Final State
M2
M0
M0
M0
M1
M2
M1
M2
Rev.1.01
Final State
Final State
State2
State2
M0
M01
SCR2=0011
SCR2=1100
M1 disabled in
range mode
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