MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 1123

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

0x0020–0x002F Debug Module (DBG)
0x0030–0x033 Reserved
0x0034–0x003F Clock and Power Management (CPMU) Map 1 of 2
Freescale Semiconductor
Address
Address
Address
0x0030-
0x002A
0x002B
0x002C
0x002D
0x002E
0x003A
0x003B
0x003C
0x0029
0x002F
0x0033
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
CPMUCLKS
DBGADHM
CPMUCOP
DBGADLM
CPMUFLG
CPMUPLL
CPMUINT
CPMURTI
DBGXAM
DBGADH
Reserved
POSTDIV
DBGXAH
DBGXAL
DBGADL
REFDIV
CPMU
CPMU
CPMU
Name
Name
Name
SYNR
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
PLLSEL
RTDEC
WCOP
Bit 15
Bit 15
Bit 15
RTIE
Bit 7
Bit 7
Bit 7
RTIF
Bit 7
Bit 7
Bit 7
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
0
0
MC9S12G Family Reference Manual, Rev.1.01
RSBCK
PORF
PSTP
RTR6
Bit 6
Bit 6
Bit 6
14
14
14
0
6
6
6
0
0
0
0
WRTMASK
RTR5
LVRF
Bit 5
Bit 5
Bit 5
FM1
13
13
13
0
5
5
5
0
0
0
0
0
0
LOCKIE
LOCKIF
RTR4
Bit 4
Bit 4
Bit 4
FM0
12
12
12
0
4
4
4
0
0
0
0
LOCK
RTR3
Bit 3
Bit 3
Bit 3
PRE
11
11
11
0
3
3
3
0
0
0
0
SYNDIV[5:0]
POSTDIV[4:0]
RTR2
Bit 2
Bit 2
Bit 2
ILAF
PCE
CR2
10
10
10
0
2
2
2
0
0
0
REFDIV[3:0]
Detailed Register Address Map
OSCSEL
OSCIF
OSCIE
Bit 17
RTR1
Bit 1
Bit 1
Bit 1
CR1
RTI
9
1
9
1
9
1
0
0
OSCSEL
UPOSC
Bit 16
RTR0
Bit 0
Bit 0
Bit 0
COP
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
CR0
0
0
0
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