MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 453

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

14.3.2.3
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0002
Reserved
ETRIGLE
ETRIGP
ETRIGE
Reset
AFFC
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
6
5
4
3
2
W
R
1
ETRIGSEL
Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior.
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 14-7
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in
input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with
external events.
0 Disable external trigger
1 Enable external trigger
1
1
1
1
ATD Control Register 2 (ATDCTL2)
0
0
7
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
ETRIGCH3
for details.
AFFC
0
0
0
1
= Unimplemented or Reserved
0
6
Table 14-5. External Trigger Channel Select Coding
Figure 14-5. ATD Control Register 2 (ATDCTL2)
MC9S12G Family Reference Manual, Rev.1.01
ETRIGCH2
Table 14-6. ATDCTL2 Field Descriptions
Reserved
X
0
0
1
5
0
Table
ETRIGCH1
14-5. If the external trigger source is one of the AD channels, the digital
ETRIGLE
X
X
1
1
0
4
Description
ETRIGCH0
ETRIGP
X
X
0
1
0
3
Analog-to-Digital Converter (ADC12B16CV2)
ETRIGE
External trigger source is
2
0
Reserved
Reserved
ETRIG2
ETRIG3
ASCIE
1
1
0
1
Table 14-7
ACMPIE
for details.
0
0
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