MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 295

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 8-22
corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution
stage of the instruction queue.
8.3.2.8.2
The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window
from 0x0028 to 0x002F as shown in
Freescale Semiconductor
Address: 0x0029
(Comparator A)
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
COMPE
Field
RWE
NDB
RW
W
R
3
2
1
0
shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the
0
0
7
Debug Comparator Address High Register (DBGXAH)
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same
register is set.
0 Write cycle is matched1Read cycle is matched
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator.This bit is ignored if the TAG bit in the same register is set
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same
register is set. This bit is only available for comparator A.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
RWE Bit
Figure 8-16. Debug Comparator Address High Register (DBGXAH)
0
0
1
1
1
1
= Unimplemented or Reserved
0
0
6
Table 8-22. Read or Write Comparison Logic Table
RW Bit
MC9S12G Family Reference Manual, Rev.1.01
Table 8-21. DBGXCTL Field Descriptions
0
0
1
1
x
x
Section Table 8-23., “Comparator Address Register Visibility
5
0
0
RW Signal
0
1
0
1
0
1
0
0
4
Description
RW not used in comparison
RW not used in comparison
0
0
3
Write data bus
Read data bus
Comment
No match
No match
2
0
0
S12S Debug Module (S12SDBG)
Bit 17
0
1
Bit 16
0
0
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