UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 163

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Cautions on alternate-function mode (input)
The input signal to the alternate-function block is low level when the PMCn.PMCnm bit is 0 due to the AND
output of the PMCn register set value and the pin level. Thus, depending on the port setting and alternate-
function operation enable timing, unexpected operations may occur. Therefore, switch between the port
mode and alternate-function mode in the following sequence.
• To switch from port mode to alternate-function mode (input)
• To switch from alternate-function mode (input) to port mode
The concrete examples are shown as Example 1 and Example 2.
[Example 1] Switch from general-purpose port (P02) to external interrupt pin (NMI)
Set the pins to the alternate-function mode using the PMCn register and then enable the alternate-
function operation.
Stop the alternate-function operation and then switch the pins to the port mode.
The order of setting in which malfunction may occur on switching from the P41 pin to the
SCL01 pin are shown below.
In <2>, I
to the pin. In the CMOS output period of <2> or <3>, unnecessary current may be generated.
<1>
<2>
<3>
<4>
Setting Order
When the P02/NMI pin is pulled up as shown in Figure 4-33 and the rising edge is specified
in the NMI pin edge detection setting, even though high level is input continuously to the NMI
pin during switching from the P02 pin to the an NMI pin (PMC02 bit = 0 → 1), this is detected
as a rising edge as if the low level changed to high level, and an NMI interrupt occurs.
To avoid it, set the NMI pin’s valid edge after switching from the P02 pin to the NMI pin.
2
C communication may be affected since the alternate-function SOB0 output is output
Initial value
(PMC41 bit = 0,
PFC41 bit = 0,
PF41 bit = 0)
PMC41 bit ← 1
PFC41 bit ← 1
PF41 bit ← 1
Setting Contents
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
Port mode (input)
SOB0 output
SCL01 I/O
SCL01 I/O
Pin States
Hi-Z
Low level (high level depending on the
CSIB0 setting)
High level (CMOS output)
Hi-Z (N-ch open-drain output)
Pin Level
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