UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 481

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

LIN
bus
RXDAn (input)
Edge detection
Notes 1. The wakeup signal is sent by the pin edge detector, UARTAn is enabled, and the SBF reception
2. The receive operation is performed until detection of the stop bit. Upon detection of SBF reception
3. If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF
4. The RXDAn pin is connected to TI (capture input) of the timer, the transfer rate is calculated, and the
5. Check-sum field distinctions are made by software. UARTAn is initialized following CSF reception,
mode is set.
of 11 or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon
detection of SBF reception of less than 11 bits, an SBF reception error is judged, no interrupt signal
is output, and the mode returns to the SBF reception mode.
reception complete interrupt. Moreover, error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE,
and UAnSTR.UAnFE bits is suppressed and UART communication error detection processing and
UARTAn receive shift register and data transfer of the UAnRX register are not performed. The
UARTAn receive shift register holds the initial value, FFH.
baud rate error is calculated. The value of the UAnCTL2 register obtained by correcting the baud
rate error after dropping UARTA enable is set again, causing the status to become the reception
status.
and the processing for setting the SBF reception mode again is performed by software.
Reception interrupt (INTUAnR)
Capture timer
Disable
Wake-up
signal
frame
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Enable
Note 1
Figure 15-7. LIN Reception Manipulation Outline
Disable
reception
Note 2
13 bits
SBF
break
Sync
Preliminary User’s Manual U18953EJ1V0UD
field
Note 3
Enable
SF reception
Sync
field
Note 4
ID reception
Identifier
field
transmission
DATA
Data
field
transmission
Data
DATA
field
Data transmission
Check
Note 5
SUM
field
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