UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 680

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.5.2 Debug trap
acknowledged.
680
A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always
(1) Operation
Upon occurrence of a debug trap, the CPU performs the following processing.
<1> Saves restored PC to DBPC.
<2> Saves current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets handler address (00000060H) for debug trap to PC and transfers control.
The debug trap processing format is shown below.
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
CPU processing
Figure 19-13. Debug Trap Processing Format
Preliminary User’s Manual U18953EJ1V0UD
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
Exception processing
DBTRAP instruction
Restored PC
PSW
1
1
1
00000060H