UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 707

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UPD70F3737GC-UEU-AX

Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3737GC-UEU-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Item
LVI
Main clock oscillator
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
Notes 1. If the STOP mode is set while the A/D converter is operating, the A/D converter is automatically stopped
2. Even if the STOP mode is set while the A/D converter is operating, the power consumption is reduced
3. If the STOP mode is set while the D/A converter is operating, the D/A converter is automatically stopped
4. Even if the STOP mode is set while the D/A converter is operating, the power consumption is reduced
and starts operating again after the STOP mode is released. However, in that case, the A/D conversion
results after the STOP mode is released are invalid. All the A/D conversion results before the STOP
mode is set are invalid.
equivalently to when the A/D converter is stopped before the STOP mode is set.
and the pin status becomes high impedance. After the STOP mode is released, D/A conversion
resumes, the setting time elapses, and the status returns to the output level before the STOP mode was
set.
equivalently to when the D/A converter is stopped before the STOP mode is set.
Setting of STOP Mode
CSIB0 to CSIB4
I
UARTA0 to UARTA2
2
C00 to I
2
C02
Table 21-8. Operating Status in STOP Mode
Operable
Stops oscillation
Oscillation enabled
Stops operation
Stops operation
Stops operation
Stops operation (but standby mode release is possible)
Stops operation
Stops operation
Operable when f
count clock
Stops operation
Operable when f
count clock
Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4)
Stops operation
Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
Stops operation (conversion result undefined)
Stops operation
Stops operation (output held)
Operable
Stops operation
See 2.2 Pin States.
Retains status before STOP mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the STOP mode was set.
CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
When Subclock Is Not Used
Notes 3, 4
R
R
/8 is selected as the
is selected as the
(high impedance is output)
Operating Status
Oscillates
Operable when f
the count clock
Operable when f
count clock
Operable when f
the count clock
Notes 1, 2
When Subclock Is Used
R
XT
R
/8 or f
or f
is selected as the
XT
XT
is selected as
is selected as
707

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