UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 575

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UPD70F3737GC-UEU-AX

Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3737GC-UEU-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
17.5 I
17.5.1 Pin configuration
resistor is required.
The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows (n = 0 to 2).
SCL0n ................ This pin is used for serial clock input and output.
SDA0n ................ This pin is used for serial data input and output.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
2
C Bus Mode Functions
Clock output
(Clock input)
Data output
Data input
Master device
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Figure 17-6. Pin Configuration Diagram
Preliminary User’s Manual U18953EJ1V0UD
SCL0n
SDA0n
CHAPTER 17 I
V
V
DD
DD
2
C BUS
SDA0n
SCL0n
Slave device
(Clock output)
Clock input
Data output
Data input
575

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