UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 530

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

530
SIBn pin capture
INTCBnR signal
(2) Operation timing
CBnSCE bit
CBnTSF bit
SCKBn pin
SOBn pin
SIBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A3H to the CBnCTL0 register, and select the reception mode, MSB first, and continuous transfer
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and start
(5) When reception is started, output the serial clock to the SCKBn pin, and capture the receive data of
(6) When reception is completed, the reception completion interrupt request signal (INTCBnR) is
(7) When the CBnCTL0.CBnSCE bit = 1 upon communication completion, the next communication is
(8) To end continuous reception with the current reception, write the CBnSCE bit = 0.
(9) Read the CBnRX register.
(10) When reception is completed, the INTCBnR signal is generated, and reading of the CBnRX register is
(11) Read the CBnRX register.
(12) If an overrun error occurs, write the CBnSTR.CBnOVE bit = 0, and clear the error flag.
(13) To release the reception enable status, write the CBnCTL0.CBnPWR bit = 0 and the
Remark
timing
f
mode at the same time as enabling the operation of the communication clock (f
reception.
the SIBn pin in synchronization with the serial clock.
generated, and reading of the CBnRX register is enabled.
started following communication completion.
enabled. When the CBnSCE bit = 0 is set before communication completion, stop the serial clock
output to the SCKBn pin, and clear the CBnTSF bit to 0, to end the receive operation.
CBnCTL0.CBnRXE bit = 0 after checking that the CBnTSF bit = 0.
XX
L
/2, and master mode.
(1)
(2)
(3)
n = 0 to 4
(4)
(5)
Bit 7 Bit 6
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 5 Bit 4
Preliminary User’s Manual U18953EJ1V0UD
Bit 3 Bit 2
Bit 1
(6) (7) (8) (9)
Bit 0
Bit 7 Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1
(10)
Bit 0
CCLK
).
(11) (13)
CCLK
) =