UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 737

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.3 Registers
The low-voltage detector is controlled by the following registers.
• Low voltage detection register (LVIM)
• Low voltage detection level select register (LVIS)
(1) Low voltage detection register (LVIM)
The LVIM register is a special register. This can be written only in the special combination of the sequences
(see 3.4.7 Special registers).
The LVIM register is used to enable or disable low voltage detection, and to set the operation mode of the low-
voltage detector.
This register can be read or written in 8-bit or 1-bit units. However, the LVIF bit is read-only.
After reset: Note 1
LVIM
Notes 1. Reset by low-voltage detection: 82H
Cautions 1. When the LVION and LVIMD bits to 1, the low-voltage detector cannot be stopped
2. Do not change the LVION bit from 1 to 0 while the supply voltage (V
3. After the LVI operation has started (LVION bit = 1) or when INTLVI has occurred, confirm
LVIF
LVION
LVION
LVIMD
2. When the LVION bit is set to 1, the comparator in the LVI circuit starts operating.
3. Be sure to set bits 6 to 2 to “0”.
<7>
Reset due to other source:
detected voltage (V
the supply voltage state by using the LVIF bit.
0
1
0
1
0
1
Notes 2, 3
until the reset request due to other than the low-voltage detection is generated.
Wait at least 0.2 ms by software before checking the voltage at the LVIF bit after
the LVION bit is set.
Disable operation.
Enable operation.
Generates interrupt request signal INTLVI when the supply voltage drops or rises
across the detected voltage.
Generate internal reset signal LVIRES when supply voltage < detected voltage.
When supply voltage > detected voltage, or when operation is disabled
Supply voltage of connected power supply < detected voltage
CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI)
R/W
6
0
Preliminary User’s Manual U18953EJ1V0UD
Address: FFFFF890H
LVI
Selection of operation mode of low voltage detection
) (LVIM.LVIF bit = 1).
Low voltage detection operation enable or disable
5
0
00H
Low voltage detection flag
4
0
3
0
0
2
LVIMD
<1>
DD
) is lower than the
LVIF
<0>
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