UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 84

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.3
Note The value written to the output latch is retained until a new value is written to the output latch.
84
Control register
Ports
(1) Port n register (Pn)
Setting of PMn Register
Port Configuration
Data is input from or output to an external device by writing or reading the Pn register.
The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register.
Output mode
(PMnm = 0)
(PMnm = 1)
Input mode
Item
Pn
After reset: 00H (output latch)
Pnm
Pn7
0
1
7
Data is written to the output latch
In the port mode (PMCn = 0), the contents of the output
latch are output from the pins.
Data is written to the output latch.
The pin status is not affected
Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CD, CM, CT, DH, DL)
Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CT, DH, DL)
Port n function control register (PFCn: n = 0, 3 to 5, 9)
Port n function control expansion register (PFCEn: n = 3, 5, 9)
Port n function register (PFn: n = 0, 3 to 5, 9)
I/O: 84
Output 0.
Output 1.
Pn6
6
Table 4-3. Writing/Reading Pn Register
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
Writing to Pn Register
Table 4-2. Port Configuration
Pn5
5
Control of output data (in output mode)
R/W
Note
Pn4
7
.
Note
.
Pn3
3
Configuration
Pn2
2
The value of the output latch is read.
The pin status is read.
Pn1
1
Reading from Pn Register
Pn0
0