UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 431

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
ADA0
FR2
0
0
0
0
1
1
1
1
Other than above
ADA0
FR1
0
0
1
1
0
0
1
1
Stabilization time:
Conversion time:
Wait time:
Trigger response time: If a software trigger, external trigger, or timer trigger is generated after the
In the normal conversion mode, the conversion is started after the stabilization time elapsed from the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.6 to
10.4
signal (INTAD) is generated after the wait time is elapsed.
Because the conversion operation is stopped during the wait time, operation current can be reduced.
Note Setting prohibited when 2.7 V ≤ AV
Cautions 1. Set as 2.6
Table 13-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0)
ADA0
μ
FR0
s). Operation is stopped after the conversion ends and the A/D conversion end interrupt request
0
1
0
1
0
1
0
1
2. During A/D conversion, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT
66/f
131/f
196/f
259/f
311/f
363/f
415/f
467/f
+ Conversion Time + Wait Time
registers are written or trigger is input, reconversion is carried out. However, if the
stabilization time end timing conflicts with the writing to these registers, or if the
stabilization time end timing conflicts with the trigger input, the stabilization time of 64
clocks is reinserted.
Set as 3.9
If a conflict occurs again with the reinserted stabilization time end timing, the
stabilization time is reinserted. Therefore do not set the trigger input interval and
control register write interval to 64 clocks or below.
XX
XX
XX
XX
XX
XX
XX
XX
(13/f
(50/f
(26/f
(39/f
(50/f
(50/f
(50/f
(50/f
Stabilization Time
XX
XX
XX
XX
XX
XX
XX
XX
A/D converter setup time (1
Actual A/D conversion time (2.6 to 10.4
Wait time inserted before the next conversion
stabilization time, it is inserted before the conversion time.
+ 26/f
+ 130/f
+ 52/f
+ 78/f
+ 104/f
+ 156/f
+ 182/f
+ 208/f
μ
μ
s ≤ conversion time ≤ 10.4
s ≤ conversion time ≤ 10.4
XX
XX
XX
Preliminary User’s Manual U18953EJ1V0UD
XX
+ 27/f
XX
XX
XX
XX
+ 53/f
+ 79/f
CHAPTER 13 A/D CONVERTER
+ 131/f
+ 105/f
+ 157/f
+ 183/f
+ 209/f
XX
XX
XX
)
)
)
XX
XX
XX
XX
XX
)
)
)
)
)
REF0
f
Setting
prohibited
6.55
9.8
12.95
15.55
18.15
20.75
23.35
XX
< 3.0 V
= 20 MHz f
μ
A/D Conversion Time
μ
s
s
μ
μ
μ
μ
μ
μ
Setting prohibited
Note
s
s
s
s
s
s or longer)
μ
μ
Setting
prohibited
8.19
12.25
16.19
19.44
22.69
Setting
prohibited
Setting
prohibited
XX
s when 2.7 V ≤ AV
s when 3.0 V ≤ AV
= 16 MHz f
μ
μ
s
μ
μ
μ
Note
s
s
s
s
μ
s)
Setting
prohibited
10.92
16.33
21.58
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
XX
= 12 MHz f
μ
μ
μ
s
s
s
REF0
REF0
6.6
13.1
19.6
25.9
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
XX
= 10 MHz f
≤ 3.6 V.
< 3.0 V.
μ
μ
μ
μ
s
s
s
s
16.5
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
XX
= 4 MHz
μ
s
Response
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
Trigger
Time
XX
XX
XX
XX
XX
XX
XX
XX
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