UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 561

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note
Remark
Condition for clearing (SPIEn bit = 0)
• Cleared by instruction
• After reset
During address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. This
bit setting becomes valid when the address transfer is completed. In master mode, a wait state is inserted at the
falling edge of the ninth clock during address transfer. For a slave device that has received a local address, a wait
state is inserted at the falling edge of the ninth clock after ACK is generated. When the slave device has received
an extension code, however, a wait state is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIMn bit = 0)
• Cleared by instruction
• After reset
The ACKEn bit setting is invalid for address reception by the slave device. In this case, ACK is generated when
the addresses match.
However, the ACKEn bit setting is valid for reception of the extension code. Set the ACKEn bit in the system that
receives the extension code.
Condition for clearing (ACKEn bit = 0)
• Cleared by instruction
• After reset
ACKEn
WTIMn
SPIEn
0
1
0
1
0
1
This flag’s signal is invalid when the IICEn bit = 0.
Note
Note
Note
n = 0 to 2
Disabled
Enabled
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and the wait state is set.
Slave mode: After input of eight clocks, the clock is set to low level and the wait state is set for the
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and the wait state is set.
Slave mode: After input of nine clocks, the clock is set to low level and the wait state is set for the
Acknowledgment disabled.
Acknowledgment enabled. During the ninth clock period, the SDA0n line is set to low level.
Enable/disable generation of interrupt request when stop condition is detected
master device.
master device.
Preliminary User’s Manual U18953EJ1V0UD
Control of wait state and interrupt request generation
CHAPTER 17 I
Acknowledgment control
2
C BUS
Condition for setting (SPIEn bit = 1)
• Set by instruction
Condition for setting (WTIMn bit = 1)
• Set by instruction
Condition for setting (ACKEn bit = 1)
• Set by instruction
(2/4)
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