UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 197

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note The CLS bit is a read-only bit.
Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being
Remark ×: don’t care
2. Use a bit manipulation instruction to manipulate the CK3 bit.
3. When the external clock is used, set the MFRC bit to “1” so as not to use the internal
After reset: 03H
PCC
output.
manipulation instruction, do not change the set values of the CK2 to CK0 bits.
feedback resistor.
•
•
•
CLS
MFRC
Even if the MCK bit is set (1) while the system is operating with the main clock as
the CPU clock, the operation of the main clock does not stop. It stops after the
CPU clock has been changed to the subclock.
Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions
operating with the main clock.
When the main clock is stopped and the device is operating with the subclock,
clear (0) the MCK bit and secure the oscillation stabilization time by software
before switching the CPU clock to the main clock or operating the on-chip
peripheral functions.
MCK
FRC
FRC
CK3
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
Note
Used
Not used
Oscillation enabled
Oscillation stopped
Used (when ceramic/crystal resonator is used)
Not used (when external clock is used)
Main clock operation
Subclock operation
CHAPTER 6 CLOCK GENERATION FUNCTION
R/W
MCK
CK2
< >
0
0
0
0
1
1
1
×
Preliminary User’s Manual U18953EJ1V0UD
Address: FFFFF828H
MFRC
CK1
0
0
1
1
0
0
1
×
Use of main clock on-chip feedback resistor
Use of subclock on-chip feedback resistor
CLS
Main clock oscillator control
Status of CPU clock (f
CK0
< >
0
1
0
1
0
1
×
×
Note
f
f
f
f
f
f
Setting prohibited
f
XX
XX
XX
XX
XX
XX
XT
CK3
< >
/2
/4
/8
/16
/32
Clock selection (f
CK2
CPU
)
CK1
CLK
/f
CPU
When using an 8-bit
)
CK0
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