UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 202

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5
6.5.1
function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral
functions.
6.5.2
202
In the V850ES/JG3-L, an operating clock that is 4 times higher than the oscillation frequency output by the PLL
When PLL function is used: Input clock = 2.5 to 5 MHz (output: 10 to 20 MHz)
Clock-through mode:
(1) PLL control register (PLLCTL)
Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clock-
PLL Function
The PLLCTL register is an 8-bit register that controls the PLL function.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
Overview
Registers
2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not
PLLCTL
through mode).
(unlocked), “0” is written to the SELPLL bit if data is written to it.
After reset: 01H
SELPLL
PLLON
0
1
0
1
0
Input clock = 2.5 to 10 MHz (output: 2.5 to 10 MHz)
CHAPTER 6 CLOCK GENERATION FUNCTION
PLL stopped
PLL operating
(After PLL operation starts, a lockup time is required for frequency stabilization)
Clock-through mode
PLL mode
R/W
0
Preliminary User’s Manual U18953EJ1V0UD
Address: FFFFF82CH
0
CPU operation clock selection register
PLL operation stop register
0
0
0
SELPLL
< >
PLLON
< >