UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 702

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.5 IDLE2 Mode
21.5.1 Setting and operation status
the normal operation mode.
other on-chip peripheral functions stops.
retained. The CPU, PLL, and other on-chip peripheral functions stop operating. However, the on-chip peripheral
functions that can operate with the subclock or an external clock continue operating.
the on-chip peripheral functions, PLL, and flash memory. However, because the PLL and flash memory are stopped,
a setup time for the PLL and flash memory is required when IDLE2 mode is released.
21.5.2 Releasing IDLE2 mode
unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal
from the peripheral functions operable in the IDLE2 mode, or reset signal (reset by RESET pin input, WDT2RES
signal, low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the operating status it was in before
the IDLE2 mode was set.
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The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in
In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and
As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are
Table 21-7 shows the operating status in the IDLE2 mode.
The IDLE2 mode can reduce the power consumption more than the IDLE1 mode because it stops the operations of
Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register
The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
After the IDLE2 mode has been released, the normal operation mode is restored.
(1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is processed as follows.
Caution The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and
(a) If an interrupt request signal with a priority lower than or equal to that of the interrupt request currently
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being
being serviced is issued, the IDLE2 mode is released, but that interrupt request signal is not
acknowledged. The interrupt request signal itself is retained.
serviced is issued (including a non-maskable interrupt request signal), the IDLE2 mode is released and
that interrupt request signal is acknowledged.
2. If the IDLE2 mode is set while an unmasked interrupt request signal is being held pending,
to set the IDLE2 mode.
the IDLE2 mode is released immediately by the pending interrupt request.
PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not released.
CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U18953EJ1V0UD