UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 509

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) CSIBn control register 1 (CBnCTL1)
CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
(n = 0 to 4)
CBnCTL1
After reset 00H
Note Set the communication clock (f
Remark
CBnCKS2
Communication
Communication
Communication
Communication
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
type 1
type 2
type 3
type 4
0
0
0
0
1
1
1
1
0
R/W
CBnCKS1
When n = 0, 1, m = 1
When n = 2, 3, m = 2
When n = 4, m = 3
For details of f
CBnCKP
0
0
1
1
0
0
1
1
0
Preliminary User’s Manual U18953EJ1V0UD
0
0
1
1
Address: CB0CTL1 FFFFFD01H, CB1CTL1 FFFFFD11H,
CBnCKS0
CBnDAP
0
1
0
1
0
1
0
1
0
1
0
1
0
BRGm
CB2CTL1 FFFFFD21H, CB3CTL1 FFFFFD31H,
CB4CTL1 FFFFFD41H
SOBn
SOBn
SIBn capture
SIBn capture
SIBn capture
SIBn capture
SCKBn
SCKBn
SCKBn
SCKBn
CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0
, see 16.8 Baud Rate Generator.
Communication clock (f
f
f
f
f
f
f
f
External clock (SCKBn)
XX
XX
XX
XX
XX
XX
BRGm
(output)
(output)
(output)
(output)
/2
/4
/8
/16
/32
/64
(I/O)
(I/O)
(I/O)
(I/O)
CCLK
reception timing in relation to SCKBn
Specification of data transmission/
D7
D7
) to 5 MHz or lower.
D7
D7
D6
D6
D6
D6
D5
D5
CCLK
D5
D5
D4
D4
)
Note
D4
D4
D3
D3
D3
D3
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
D2
D2
D2
D2
Mode
D1
D1
D1
D1
D0
D0
D0
D0
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