UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 337

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(e) TMQ0 counter read buffer register (TQ0CNT)
(f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
The value of the 16-bit counter can be read by reading the TQ0CNT register.
If D
to the TQ0CCR3 register, the cycle and active level of the PWM waveform are as follows.
Remarks 1. TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not
Cycle = (D
TOQ01 pin PWM waveform active level width = D
TOQ02 pin PWM waveform active level width = D
TOQ03 pin PWM waveform active level width = D
0
is set to the TQ0CCR0 register, D
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (3/3)
2. Updating TMQ0 capture/compare register 2 (TQ0CCR2) and TMQ0 capture/compare
0
+ 1) × Count clock cycle
used in the external trigger pulse output mode.
register 3 (TQ0CCR3) is validated by writing TMQ0 capture/compare register 1 (TQ0CCR1).
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Preliminary User’s Manual U18953EJ1V0UD
1
to the TQ0CCR1 register, D
1
2
3
× Count clock cycle
× Count clock cycle
× Count clock cycle
2
to the TQ0CCR2 register, and D
337
3
,