UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 335

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOQ0k pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOQ00 pin is inverted. The TOQ0k pin outputs a high-level regardless of the status
(high/low) when a trigger is generated.)
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTQ0CCk is generated when the count value of the 16-bit counter matches the value
of the CCRk buffer register.
bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H.
used as the trigger.
TQ0CTL0
TQ0CTL1
16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal INTTQ0CC0 is generated when the 16-bit counter counts next time after its
The value set to the TQ0CCRm register is transferred to the CCRm buffer register when the count value of the 16-
The valid edge of an external trigger input signal, or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is
Remark
Active level width = (Set value of TQ0CCRk register) × Count clock cycle
Cycle = (Set value of TQ0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TQ0CCRk register)/(Set value of TQ0CCR0 register + 1)
(a) TMQ0 control register 0 (TQ0CTL0)
(b) TMQ0 control register 1 (TQ0CTL1)
k = 1 to 3
m = 0 to 3
TQ0CE
0/1
0
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (1/3)
TQ0EST
0/1
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0EEE
0
0
Preliminary User’s Manual U18953EJ1V0UD
0
0
0
0
TQ0CKS2 TQ0CKS1 TQ0CKS0
TQ0MD2 TQ0MD1 TQ0MD0
0/1
0
0/1
1
0/1
0
0, 1, 0:
External trigger pulse
output mode
Select count clock
0: Stop counting
1: Enable counting
0: Operate on count
Generate software trigger
when 1 is written
clock selected by
TQ0CKS0 to TQ0CKS2 bits
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