UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 570

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

570
(5) IIC function expansion registers 0 to 2 (IICX0 to IICX2)
(6) I
The IICXn register sets I
These registers can be read or written in 8-bit or 1-bit units.
Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register
and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 17.4 (6) I
setting method) (m = 0, 1).
Set the IICXn register when the IICCn.IICEn bit = 0.
Reset sets these registers to 00H.
The I
For example, the I
ns is calculated using following expression.
The clock to be selected can be set by the combination of the SMCn, CLn1, and CLn0 bits of the IICCLn
register, the CLXn bit of the IICXn register, and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm
register (n = 0 to 2, m = 0, 1).
2
C0n transfer clock setting method
f
2
SCL
C0n transfer clock frequency (f
IICXn
(n = 0 to 2)
m = 12, 18, 24, 36, 44, 48, 54, 60, 66, 72, 86, 88, 96, 132, 172, 176, 198, 220, 258, 344 (see Table
T:
t
t
f
After reset: 00H
R
F
SCL
= 1/(m × T + t
:
:
= 1/(198 × 52 ns + 200 ns + 50 ns) ≅ 94.7 kHz
17-2 Clock Settings).
1/f
SCL0n pin rise time
SCL0n pin fall time
SCL0n
XX
2
SCL0n inversion
C0n transfer clock frequency (f
0
R
t
R
2
+ t
C0n function expansion (valid only in the high-speed mode).
R/W
F
)
0
m/2 × T
Preliminary User’s Manual U18953EJ1V0UD
Address: IICX0 FFFFFD85H, IICX1 FFFFFD95H, IICX2 FFFFFDA5H
SCL
) is calculated using the following expression (n = 0 to 2).
0
CHAPTER 17 I
m × T + t
SCL0n inversion
0
R
SCL
+ t
F
) when f
t
2
F
C BUS
0
m/2 × T
XX
= 19.2 MHz, m = 198, t
0
SCL0n inversion
0
CLXn
< >
R
= 200 ns, and t
2
C0n transfer clock
F
= 50