UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 55

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UPD70F3737GC-UEU-AX

Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3737GC-UEU-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
3.3
3.3.1
programmer is connected, but it must be input from an external circuit in the self-programming mode.
The V850ES/JG3-L has the following operation modes.
(1) Normal operation mode
(2) Flash memory programming mode
(3) On-chip debug mode
Specify the operation mode by using the FLMD0 and FLMD1 pins.
In the normal mode, make sure that a low level is input to the FLMD0 pin when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
Operation Modes
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
In this mode, the internal flash memory can be programmed by using a flash programmer.
The V850ES/JG3-L is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group)
communication specifications.
For details, see CHAPTER 29 ON-CHIP DEBUG FUNCTION.
Specifying operation mode
Remark
Operation When Reset Is Released
FLMD0
H
H
L
L: Low-level input
H: High-level input
×: Don’t care
FLMD1
Preliminary User’s Manual U18953EJ1V0UD
H
×
L
CHAPTER 3 CPU FUNCTION
Normal operation mode
Flash memory programming mode
Setting prohibited
Operation Mode After Reset
55

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