UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 352

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

352
<1> Count operation start flow
TQ0CCR0 to TQ0CCR3 registers
(TQ0CKS0 to TQ0CKS2 bits)
Register initial setting
TQ0CTL1 register,
TQ0IOC0 register,
TQ0IOC2 register,
TQ0CTL0 register
Remark
TQ0CE bit = 1
START
Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2)
m = 0 to 3
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Initial setting of these
registers is performed
before setting the
TQ0CE bit to 1.
The TQ0CKS0 to
TQ0CKS2 bits can be
set at the same time
when counting has been
started (TQ0CE bit = 1).
Trigger wait status
Preliminary User’s Manual U18953EJ1V0UD
<2> TQ0CCR0 to TQ0CCR3 register setting change flow
<3> Count operation stop flow
Setting of TQ0CCR0 to TQ0CCR3
TQ0CE bit = 0
registers
STOP
Count operation is
stopped
As rewriting the
TQ0CCRm register
immediately forwards
to the CCRm buffer
register, rewriting
immediately after
the generation of the
INTTQ0CCR0 signal
is recommended.